View MAX3950EGK-TD_7317004.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max3950 deserializer is ideal for converting 10gbps serial data to 16-bit-wide, 622mbps parallel data in sdh/sonet and dwdm applications. operating from a single +3.3v supply, this device accepts cml serial clock and data inputs and delivers low-voltage differential-signal (lvds) clock and data outputs for interfacing with high-speed digital circuitry. the max3950 is available in the extended temperature range (-40? to +85?) in a 68-pin qfn package. the typical power dissipation is 900mw. applications sonet/oc-192 sdh/stm-64 transmission systems add/drop multiplexers broadband digital cross-connects features ? supports serial data rates up to 10.7gbps ? 10gbps/10.7gbps serial to 622mbps/667mbps parallel conversion ? single +3.3v supply ? 900mw operating power ? cml serial clock and data inputs ? lvds parallel clock and data outputs ? -40c to +85c operating temperature max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs ________________________________________________________________ maxim integrated products 1 19-1853; rev 2; 7/06 ordering information 68 qfn pin-package temp range -40? to +85? max3950egk part pin configuration appears at the end of data sheet. this symbol represents a transmission line of characteristic impedance z o = 50 ? . sd+ sd- sclk+ sclk- pd15+ pd15- pd0+ pd0- *required only if overhead circuit does not include internal input termination. pclk+ pclk- overhead processing 10gbps 622mbps v cc 100 ? * 100 ? * 100 ? * max3950 deserializer typical application circuit for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, differential loads = 100 ? ?%, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. positive supply voltage (v cc )...............................-0.5v to +5.0v cml input voltage level .................(v cc - 0.8v) to (v cc + 0.5v) lvds output voltage level........................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85?) 68-lead qfn (derate 43.5mw/? above +85?) ......2800mw operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply current i cc 270 350 ma cml inputs (sd , sclk ) differential input voltage swing v id 400 1200 m v p-p single-ended input voltage range v is figure 1 v cc - 0.6 v c c + 0.3 v input termination to v cc r in 42.5 50 57.5 ? lvds output specification (pd[15.0] , pclk ) output high voltage v oh 1.375 v output low voltage v ol 1.025 v differential output voltage | v od | figure 2 150 250 mv change in magnitude of differential output for complementary states ? | v od | 25 mv offset output voltage 1.15 1.25 v change in magnitude of output offset voltage for complementary states ? | v os | 25 mv differential output impedance 80 120 ? short together 12 output current short to ground 24 ma
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +3.6v, differential loads = 100 ? ?%, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units serial input data rate 10 gbps serial data setup time t su 25 ps serial data hold time t h 25 ps parallel output data rate 622 mbps parallel output clock frequency 622 mhz parallel clock-to-q delay t clk-q (note 2) -200 +200 ps lvds output rise/fall time 20% to 80% 300 ps lvds differential skew t skew1 any differential pair 65 ps lvds channel-to-channel skew t skew2 pd[15..0] f 5ghz 17 5ghz f 10ghz 14 input return loss | s 11 | 10ghz f 15ghz 11 db note 1: ac specifications are guaranteed by design and characterization. note 2: relative to the falling edge of pclk+. see figure 3. (a) ac-coupled cml input (b) dc-coupled cml input 600mv 600mv 200mv 200mv v cc v cc v cc + 0.3v v cc - 0.3v v cc - 0.6v figure 1. input amplitude
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs 4 _______________________________________________________________________________________ pd+ r l = 100 ? pd- single-ended output differential output v v od v od p-p = 2iv od i iv od i v pd- v pd+ v pd+ - v pd- v os v ol 0 v oh figure 2. driver output levels t su t h t clk sd sclk+ pclk+ pd t clk-q figure 3. timing parameters
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs _______________________________________________________________________________________ 5 -30 -20 -25 -10 -15 -5 0 010 51520 input return loss max3950 toc05 frequency (ghz) return loss (db) note: data is from simulation and includes package parasitics. typical operating characteristics (t a = +25?, unless otherwise noted.) pin name function 1, 2, 5, 13, 16, 17, 18, 26, 33?6, 42, 51, 52, 53, 60, 68 gnd ground 6, 9, 12, 25, 31, 32, 37, 43, 50, 54, 55, 61 v cc positive power supply 7 sd+ positive data input. 9.953gbps serial data stream, cml. 8 sd- negative data input. 9.953gbps serial data stream, cml. 10 sclk+ positive serial clock input. 9.953ghz, cml. 11 sclk- negative serial clock input. 9.953ghz, cml. 14 pclk- negative parallel clock output, 622.08mhz, lvds. pin description 150 180 170 160 200 190 240 230 220 210 250 -40-200 20406080 lvds output amplitude vs. temperature max3950 toc01 ambient temperature ( c) single-ended lvds output (mv p-p ) 0 50 150 100 250 200 300 -40 -20 0 20 40 60 80 output rise/fall time vs. temperature max3950 toc02 ambient temperature ( c) rise/fall time (ps) data clock note: measured 20 to 80% . output eye diagram input: 9.953gbps, 2 13 - 1 +100 zeros prbs max3950 toc03 200ps/div pclk- pd pclk+ output eye diagram input: 10.7gbps, 2 13 - 1 +100 zeros prbs max3950 toc04 200ps/div pclk- pd pclk+
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs 6 _______________________________________________________________________________________ detailed description the max3950 deserializer implements a shift-register- based demultiplexer to convert 9.953gbps serial data to 16-bit-wide, 622.08mbps parallel data (figure 4). the allocation of the serial input bits to the parallel lvds outputs is displayed in figure 5. applications information low-voltage differential-signal outputs the max3950 features lvds outputs for interfacing with high-speed digital circuitry. this lvds implementa- tion is based on the ieee 1596.3 lvds reduced-range link specification and is compatible with oif 1999.102. note that the pclk polarity on the max3950 is inverted relative to oif 1999.102, so that pclk+ is equivalent to rxclk_n and pclk- is equivalent to rxclk_p. the max3950 uses 300mv p-p to 500mv p-p differential low-voltage swings to achieve fast transition times, min- imize power dissipation, and improve noise immunity. the parallel clock and data lvds outputs (pclk+, pclk-, pd_+, pd_-) require 100 ? differential dc termi- nation between the inverting and noninverting outputs for proper operation. do not terminate these outputs to ground. for more information on interfacing with the lvds outputs, refer to maxim application note hfan- 1.0: interfacing between cml, pecl, and lvds . pin name function 15 pclk+ positive parallel clock output, 622.08mhz, lvds. 19, 21, 23, 27, 29, 38, 40, 44, 46, 48, 56, 58, 62, 64, 66, 3 pd0- to pd15- negative parallel data output, 622.08mbps, lvds. 20, 22, 24, 28, 30, 39, 41, 45, 47, 49, 57, 59, 63, 65, 67, 4 pd0+ to pd15+ positive parallel data output, 622.08mbps, lvds. ep exposed pad ground. this must be soldered to the circuit board ground for proper thermal and electrical operation. see layout considerations. cp corner pins n.c. not connected. ensure that the solder mask is located below them so that unintentional connections do not occur. pin description (continued) cml input cml input d flip-flop delay divide by 4 clk data 4-bit shift register 4-bit shift register 4-bit shift register 4-bit shift register clk output register divide by 4 data max3950 figure 4. functional block diagram
current mode logic (cml) inputs the differential serial inputs to the max3950 are cml and have an input impedance of 50 ? on each of the complementary inputs. for more information on inter- facing with the cml inputs, refer to maxim application note hfan-1.0: interfacing between cml, pecl, and lvds . interface models figures 6 and 7 show the typical input/output models for the max3950 deserializer. layout considerations for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the max3950? high-speed inputs and out- puts. place power-supply decoupling as close to v cc as possible. to reduce feedthrough, isolate the input signals from the output signals. max3950 _______________________________________________________________________________________ 7 sd pclk+ d0 d15 d14 d13 d16 d32 d48 d64 (lsb) pd0 d1 d17 d33 d49 d65 pd1 d15 (msb) transmitted first d31 d47 d63 d79 pd15 figure 5. timing diagram sd- sd+ 50 ? 1.1nh k = 0.4 1.1nh note: parasitic values shown are typical values. 70ff 70ff 250ff 250ff 50 ? high z high z v cc figure 6. cml input model +3.3v, 10.7gbps 1:16 deserializer with lvds outputs
max3950 chip information transistor count: 4800 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs 8 _______________________________________________________________________________________ max3950 v cc v cc pd_+ pd_- v cc figure 7. lvds output model 62 63 64 65 66 58 59 60 61 67 41 42 43 44 45 46 47 48 49 50 sclk- pd0+ pd14+ qfn* top view pd14- pd13+ pd13- pd12+ pd12- v cc gnd pd11+ pd11- 56 57 52 53 54 55 pd10+ pd10- v cc v cc gnd gnd pd0- pd1+ pd1- pd2+ pd2- gnd v cc pd3+ pd3- pd4+ pd4- v cc v cc gnd gnd v cc pd9+ pd9- pd8+ pd8- pd7+ pd7- v cc gnd pd6+ 35 36 37 38 39 40 pd6- pd5+ pd5- v cc gnd gnd sclk+ v cc sd- sd+ v cc gnd gnd pclk+ pclk- gnd v cc gnd pd15+ pd15- gnd 51 gnd gnd 68 gnd gnd n.c. n.c. n.c. n.c. 24 23 22 21 20 28 27 26 25 19 30 29 34 33 32 31 18 *exposed pad is connected to gnd. 11 10 9 8 7 6 5 4 3 2 17 16 15 14 13 12 1 max3950 pin configuration
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs _______________________________________________________________________________________ 9 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3950 +3.3v, 10.7gbps 1:16 deserializer with lvds outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) revision history rev 0; 11/00: initial data sheet release. rev 1; 12/02: page 6, pin configuration: corner pins changed from ground to n.c.; page 8, pin configuration: changed gnd corner pins to n.c. rev 2; 7/06: page 1: removed future products from typical application circuit.
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max3950 part number table notes: see the max3950 quickview data sheet for further information on this product family or download the max3950 full data sheet (pdf, 392kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis MAX3950EGK-TD -40c to +85c rohs/lead-free: no max3950egk-d qfn;68 pin;10x10x0.9mm dwg: 21-0103d (pdf) use pkgcode/variation: g6800-1f * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

▲Up To Search▲

Price & Availability of MAX3950EGK-TD

	To Download MAX3950EGK-TD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .